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71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
Interrupt Priority 0 Register ( IP0 ):
MSB
LSB
--
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
Table 30: The IP0 Register (see also Table 45)
Bit
IP0.6
Symbol
WDTS
Function
Watchdog timer status flag. Set when the watchdog timer was started. Can be
read by software.
Table 31: The IP0 bit Functions (see also Table 45)
Note: The remaining bits in the IP0 register are not used for watchdog control
Watchdog Timer Reload Register ( WDTREL ):
MSB
LSB
7
6
5
4
3
2
1
0
Table 32: The WDTREL Register
Bit
WDTREL .7
WDTREL .6
to
WDTREL .0
Symbol
7
6-0
Function
Prescaler select bit. When set, the watchdog is clocked through an additional
divide-by-16 prescaler
Seven bit reload value for the high-byte of the watchdog timer. This value is
loaded to the WDT when a refresh is triggered by a consecutive setting of bits
WDT and SWDT .
Table 33: The WDTREL Bit Functions
The WDTREL register can be loaded and read at any time.
Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special
function register ( TCON , IRCON , and SCON ). Each interrupt requested by the corresponding flag can be individually enabled or
disabled by the enable bits in SFRs IEN0 , IEN1 , and IEN2 .
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the
71M6521BE, for example the CE, DIO, EEPROM interface.
Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 52. Once interrupt service has
begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction,
"RETI". When an RETI is performed, the processor will return to the instruction that would have been next when the interrupt
occurred.
V1.0
? 2005-2008 TERIDIAN Semiconductor Corporation
Page: 29 of 97
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